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january 2015 docid027251 rev 2 1 / 14 this is information on a product in full production. www.st.com stf25n60m2 - ep n - channel 600 v, 0.175 typ., 18 a mdmesh? m2 ep power mosfet in a to - 220fp package datasheet - production data figure 1 : internal schematic diagram features order code v ds @ t jmax r ds(on) max. i d stf25n60m2 -ep 650 v 0.188 18 a ? extremely low gate charge ? excellent output capacitance (c oss ) profile ? very low turn - off switching losses ? 100% avalanche tested ? zener - protected applications ? switching applications ? tailored for very high frequency converters (f > 150 khz) description this device is an n - channel power mosfet developed using mdmesh? m2 ep enhanced performance technology. thanks to its strip layout and an improved vertical structure, the device exhibits low on - resistance, optimized switching characteristics with very low turn - off switching losses, rendering it suitable for the most demanding very high frequency converters. table 1: device summary order code marking package packaging stf25n60m2 -ep 25n60m2ep to - 220fp tube t o-220f p 1 2 3
contents stf25n60m2 - ep 2 / 14 docid027251 rev 2 contents 1 electrical ratings ............................................................................. 3 2 electrical characteristics ................................................................ 4 2.1 electrical characteristics (curves) ...................................................... 6 3 test circuits ..................................................................................... 9 4 package mechanical data ............................................................. 10 4.1 to - 220fp package information ...................................................... 11 5 revision history ............................................................................ 13
stf25n60m2 - ep electrical ratings docid027251 rev 2 3 / 14 1 electrical ratings table 2: absolute maximum ratings symbol parameter value unit v gs gate - source voltage 25 v i d drain current (continuous) at t c = 25 c 18 (1) a i d drain current (continuous) at t c = 100 c 11.3 (1) a i dm (2) drain current (pulsed) 72 (1) a p tot total dissipation at t c = 25 c 30 w dv/dt (3) peak diode recovery voltage slope 15 v/ns dv/dt (4) mosfet dv/dt ruggedness 50 v/ns v iso insulation withstand voltage (rms) from all three leads to external heat sink (t = 1 s, t c = 25 c) 2500 v t stg storage temperature - 55 to 150 c t j max. operating junction temperature notes: (1) limited limited by maximum junction temperature. (2) pulse width limited by safe operating area. (3) i sd 18 a, di/dt 400 a/s; v ds peak < v (br)dss , v dd = 400 v. (4) v ds 480 v table 3: thermal data symbol parameter value unit r thj - case thermal resistance junction - case max 4.2 c/w r thj - amb thermal resistance junction - ambient max 62.5 c/w table 4: avalanche characteristics symbol parameter value unit i ar avalanche current, repet i tive or not repet i tive (pulse width limited by t jmax ) 3.5 a e as single pulse avalanche energy (starting t j = 25 c, i d = i ar ; v dd = 50 v) 200 mj
electrical characteristics stf25n60m2 - ep 4 / 14 docid027251 rev 2 2 electrical characteristics t c = 25 c unless otherwise specified table 5: on/off states symbol parameter test conditions min. typ. max. unit v (br)dss drain - source break down voltage v gs = 0 v, i d = 1 ma 600 v i dss zero gate voltage drain current v gs = 0 v, v ds = 600 v 1 a v gs = 0 v, v ds = 600 v, t c = 125 c 100 a i gss gate - body leakage current v ds = 0 v, v gs = 25 v 10 a v gs(th) gate threshold voltage v ds = v gs , i d = 250 a 2 3 4 v r ds(on) static drain - source on- resistance v gs = 10 v, i d = 9 a 0.175 0.188 table 6: dynamic symbol parameter test conditions min. typ. max. unit c iss input capacitance v ds = 100 v, f = 1 mhz, v gs = 0 v - 1090 - pf c oss output capacitance - 56 - pf c rss reverse transfer capacitance - 1.6 - pf c oss eq. (1) equivalent output capacitance v ds = 0 to 480 v, v gs = 0 v - 255 - pf r g intrinsic gate resistance f = 1 mhz, i d = 0 a - 7 - q g total gate charge v dd = 480 v, i d = 18 a, v gs = 10 v (see figure 16: "gate charge test circuit" ) - 29 - nc q gs gate - source charge - 6 - nc q gd gate - drain charge - 12 - nc notes: (1) c oss eq. is defined as a constant equivalent capacitance giving the same charging time as c oss when v ds increases from 0 to 80% v dss table 7: switching energy symbol parameter test conditions min. typ. max. unit e (off) turn - off energy (from 90% v gs to 0% i d ) v dd = 400 v, i d = 2 a r g = 4.7 ?, v gs = 10 v - 7 - j v dd = 400 v, i d = 4 a r g = 4.7 ?, v gs = 10 v - 8 - j
stf25n60m2 - ep electrical characteristics docid027251 rev 2 5 / 14 table 8: switching times symbol parameter test conditions min. typ. max. unit t d(on) turn - on delay time v dd = 300 v, i d = 9 a r g = 4.7 , v gs = 10 v (see figure 15: "switching times test circuit for resistive load" and figure 20: "switching time waveform" ) - 15 - ns t r rise time - 10 - ns t d(off) turn - off- delay time - 61 - ns t f fall time - 16 - ns table 9: source drain diode symbol parameter test conditions min. typ. max. unit i sd source - drain current - 18 a i sdm (1) source - drain current (pulsed) - 72 a v sd (2) forward on voltage v gs = 0 v, i sd = 18 a - 1.6 v t rr reverse recovery time i sd = 18 a, di/dt = 100 a/s, v dd = 100 v (see figure 17: " test circuit for inductive load switching and diode recovery times" ) - 360 ns q rr reverse recovery charge - 5 c i rrm reverse recovery current - 28 a t rr reverse recovery time i sd = 18 a, di/dt = 100 a/s, v dd = 100 v, t j = 150 c (see figure 17: " test circuit for inductive load switching and diode recovery times" ) - 445 ns q rr reverse recovery charge - 6.5 c i rrm reverse recovery current - 29 a notes: (1) pulse width is limited by safe operating area (2) pulsed: pulse duration = 300 s, duty cycle 1.5%
electrical characteristics stf25n60m2 - ep 6 / 14 docid027251 rev 2 2.2 electrical characteristics (curves) figure 2 : safe operating area figure 3 : thermal impedance figure 4 : output characteristics figure 5 : transfer characteristics figure 6 : gate charge vs gate - source voltage figure 7 : static drain - source on - resistance gipg02122014 11 18als i d (a) 10 1 0.1 0.1 1 100 v ds (v) 10 10s 100s 1ms 10ms operation in this area is limited by max r ds(on) t j =150c t c =25c single pulse i d (a) 15 10 5 0 0 8 v ds (v) 4 12 20 25 30 35 40 16 v gs = 6,7,8,9,10 v v g s = 5 v v g s = 4 v gipg0 1 1220141438als gipg28 1 1201416 1 1als i d (a) 5 0 0 4 v gs (v) 8 2 6 10 15 v ds = 16 v 20 25 30 35 40 6 4 2 0 0 5 20 8 10 15 10 25 300 200 100 0 400 500 12 30 600 v dd = 480 v v ds v gs (v) q g (nc) v ds (v) gipg0 1 1220140958als 0.177 0.174 0.171 0.168 0 4 12 8 16 0.180 0.183 0.186 v gs = 10 v r ds(on) () i d (a) gipg0 1 1220141210als
stf25n60m2 - ep electrical characteristics docid027251 rev 2 7 / 14 figure 8 : capacitance variations figure 9 : output capacitance stored energy figure 10 : turn - off switching loss vs drain current figure 11 : normalized gate threshold voltage vs temperature figure 12 : normalized on - resistance vs temperature figure 13 : source - drain diode forward characteristics 1000 100 10 1 0.1 10 v ds (v) 1 100 c iss c oss c rss c (pf) gipg18 1 120141549als 2 0 0 100 v ds (v) 400 200 300 4 500 600 6 8 e oss (j) gipg18 1 120141603als 6 4 0 1 i d (a) 4 2 3 8 5 6 10 12 e oss (j) gipg26 1 12014 1 106als 0.9 0.8 0.7 0.6 -75 -25 t j (c) 1.0 25 75 125 i d = 250 a 1.1 v gs(th) (norm) gipg18 1 120141615als 1.4 1.0 0.6 0.2 -75 t j (c) -25 75 25 125 1.8 2.2 v gs = 10 v r ds(on) (norm) gipg18 1 120141628als 0 4 i sd (a) 8 0 0.6 0.7 0.9 0.8 1.0 1.1 t j =-50c t j =-50c t j =-50c 12 16 v sd (v) gipg19 1 120141427als
electrical characteristics stf25n60m2 - ep 8 / 14 docid027251 rev 2 gipg19 1 120141457als -75 t j (c) -25 75 25 125 0.88 0.92 0.96 1.04 1.00 1.08 i d = 1m a v (br)dss (norm) figure 14 : normalized v(br)dss vs temperature
stf25n60m2 - ep test circuits docid027251 rev 2 9 / 14 3 test circuits figure 15 : switching times test circuit for resistive load figure 16 : gate charge test circuit figure 17 : test circuit for inductive load switching and diode recovery times figure 18 : unclamped inductive load test circuit figure 19 : unclamped inductive waveform figure 20 : switching time waveform am01469v1 v dd 47 k 1 k 47 k 2.7 k 1 k 12 v v i v gs 2200 f p w i g = const 100 100 nf d.u.t. v g v (b r )d s s v dd v dd v d i dm i d am01472v1 am01473v1 0 v gs 90% v ds t on 90% 10% 90% 10% t d(on) t r t t d(off) t f 10% 0 off
package mechanical data stf25n60m2 - ep 10 / 14 docid027251 rev 2 4 package mechanical data in order to meet enviro nmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trad emark.
stf25n60m2 - ep package mechanical data docid027251 rev 2 11 / 14 4.1 to - 220fp package information figure 21 : to - 220fp package outline 7012510_ r ev_k_b
package mechanical data stf25n60m2 - ep 12 / 14 docid027251 rev 2 table 10: to - 220fp mechanical data dim. mm min. typ. max. a 4.4 4.6 b 2.5 2.7 d 2.5 2.75 e 0.45 0.7 f 0.75 1 f1 1.15 1.70 f2 1.15 1.70 g 4.95 5.2 g1 2.4 2.7 h 10 10.4 l2 16 l3 28.6 30.6 l4 9.8 10.6 l5 2.9 3.6 l6 15.9 16.4 l7 9 9.3 dia 3 3.2
stf25n60m2 - ep revision history docid027251 rev 2 13 / 14 5 revision history table 11: document revision history date revision changes 02- dec - 2014 1 first release. 12- jan - 2015 2 updated product status from ?preliminary data? to ?production data?. 14- jan - 2015 3 corrected product status information on cover page.
stf25n60m2 - ep 14 / 14 docid027251 rev 2 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications , and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant information on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of or der acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and s t assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information se t forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2015 stmicroelectronics ? all rights reserved

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